TLDR: Piano is a novel floorplanning framework for VLSI physical design that simultaneously optimizes module placement and pin assignment under multiple constraints, including fixed-outline, whitespace removal, and pre-placed modules. It uses a graph-based method for pin assignment and employs incremental optimization techniques like whitespace removal and local operators. Experimental results show significant reductions in wirelength, feedthrough, and unplaced pins compared to traditional methods, while achieving zero whitespace.
In the intricate world of Very Large Scale Integration (VLSI) physical design, floorplanning stands as the foundational first step. It involves strategically arranging large circuit modules on a chip and assigning connection points, known as pins, to their boundaries. This initial layout is crucial as it sets the stage for subsequent detailed placement and routing, directly impacting the chip’s overall performance.
Traditionally, floorplanning and pin assignment have been treated as separate, sequential processes. Modules are placed first, and then pins are assigned based on that layout. This separation often leads to less-than-ideal outcomes, such as unnecessarily long or congested wiring, because the impact of pin positions on inter-module connections isn’t considered during the initial placement phase. Furthermore, modern chip designs introduce complex constraints, including fixed-outline requirements, the need to eliminate unused space (whitespace removal), and the presence of pre-placed modules (PPMs) that cannot be moved.
Addressing these challenges, a new framework called Piano has been introduced. Developed by researchers from the University of Science and Technology of China and Noah’s Ark Lab, Huawei, Piano is a multi-constraint pin assignment-aware floorplanner. Its core innovation lies in simultaneously optimizing both module placement and pin assignment, all while adhering to the various modern design constraints. This integrated approach aims to overcome the limitations of traditional methods, leading to more efficient and higher-quality chip designs.
How Piano Works
Piano operates through a sophisticated three-stage framework:
The first stage, **Initialization**, prepares the circuit for optimization. It involves legalizing the floorplan by partitioning the chip canvas into a grid and assigning each grid cell to a module, effectively eliminating overlaps. This stage also reorganizes the netlist, breaking down complex connections into simpler two-module nets, which helps in accurately calculating feedthroughs – connections that pass through intermediate modules.
The second stage focuses on **Pin Assignment**. Given a legal layout, Piano constructs a graph based on the available connection resources between modules. It then uses advanced algorithms, including A* search, to find the shortest paths for pin assignments. This graph-based method is crucial for determining where pins should be placed and for evaluating metrics like feedthrough wirelength and the number of unplaced pins. Feedthrough occurs when a connection between two modules must pass through one or more other modules, which can disrupt internal component placement.
The third stage, **Incremental Optimization**, refines the design. It begins with a whitespace removal strategy to achieve a zero-whitespace layout, which allows for more effective pin reallocation and improves routability. Following this, Piano employs three specialized local optimizers: a random exchange operator for swapping non-adjacent modules, an adjacent exchange operator for reconfiguring adjacent modules while preserving their areas, and a P2PRes enhancement operator that increases the available pin-to-pin connection resources between adjacent modules. These operators work within a simulated annealing framework to iteratively improve the floorplan, aiming to minimize feedthrough and unplaced pins.
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Key Contributions and Results
Piano’s concurrent optimization of module placement and pin assignment under multiple design constraints is a significant advancement. Its graph-based algorithm for pin assignment provides accurate evaluations of feedthrough and unplaced pins, guiding the overall layout quality. The use of local operators and whitespace removal further enhances the design metrics.
Experimental results on widely used benchmark circuits demonstrate Piano’s effectiveness. It achieved an average 6.81% reduction in Half-Perimeter Wirelength (HPWL), a 13.39% decrease in feedthrough wirelength, a 16.36% reduction in the number of feedthrough modules, and a notable 21.21% drop in unplaced pins, all while maintaining zero whitespace. Furthermore, Piano can serve as an incremental optimizer for existing floorplanning algorithms, significantly enhancing their solutions, and effectively handles pre-placed modules, a common requirement in modern designs.
This work offers a fresh perspective for future research in pin assignment during the floorplanning stage, aligning more closely with practical electronic design automation (EDA) requirements. For more in-depth information, you can read the full research paper here.
