TLDR: AIGer is a novel deep learning model designed to improve the efficiency of Electronic Design Automation (EDA) by optimizing the modeling of And-Inverter Graphs (AIGs). It addresses challenges in jointly capturing functional and structural circuit characteristics and dynamic information propagation. AIGer features a unique node logic feature initialization embedding component and a heterogeneous graph convolutional network for feature learning. Experimental results demonstrate that AIGer significantly outperforms existing state-of-the-art models in Signal Probability Prediction (SPP) and Truth Table Distance Prediction (TTDP) tasks, while also optimizing training time, making it a highly effective solution for logic circuit design.
The world of electronic design automation, or EDA, is constantly evolving, driven by the need for faster, more efficient, and more reliable computer chips. A crucial part of this process involves designing and optimizing digital circuits. A common way to represent these circuits is through something called And-Inverter Graphs, or AIGs. These graphs simplify complex Boolean functions using only AND and Inverter (NOT) gates, making them easier to work with for tasks like logic synthesis and verification.
However, real-world AIGs can be incredibly complex, with a vast number of interconnected nodes. This complexity makes it challenging to accurately model them, especially when trying to capture both their functional characteristics (what the logic gates actually do) and their structural characteristics (how they are connected). Existing methods often struggle with these aspects, particularly in propagating information dynamically through the circuit’s intricate paths.
To tackle these challenges, researchers have introduced a new model called AIGer. The goal of AIGer is to significantly enhance how AIGs are represented and understood, thereby boosting the efficiency of EDA development. AIGer achieves this through two main components.
The first component is the Node Logic Feature Initialization Embedding. Imagine each type of logic gate, like an AND gate or a NOT gate, having its own unique ‘semantic space’. AIGer projects these logic nodes into these separate spaces. This allows the model to effectively distinguish between the different functions of these nodes right from the start, rather than treating them all as similar. It even considers the two logical states (0 and 1) for each node, encoding their operational characteristics explicitly.
Building on this, the second component is the AIGs Feature Learning Network. This part uses a sophisticated type of neural network designed for graphs, called a heterogeneous graph convolutional network. It’s ‘heterogeneous’ because it understands that different connections (edges) in the AIG represent different relationships. AIGer designs dynamic weight matrices for each type of connection and uses different ways to combine information from neighboring nodes. This intelligent approach helps the model better represent the original structure and information flow within the AIGs. It also includes smart strategies to reduce the number of parameters, making the model more efficient without sacrificing accuracy, especially for large and complex circuits.
The combination of these two components significantly improves AIGer’s ability to jointly model both the functional and structural aspects of AIGs. It also enhances its ‘message passing’ capability, meaning information flows more effectively through the network, leading to a stronger and more expressive representation of the circuits.
Experimental results have shown AIGer’s impressive performance. In the Signal Probability Prediction (SPP) task, which is crucial for circuit optimization, AIGer outperformed the best existing models, improving Mean Absolute Error (MAE) by 18.95% and Mean Squared Error (MSE) by 44.44%. For the Truth Table Distance Prediction (TTDP) task, which assesses functional similarity between nodes, AIGer achieved improvements of 33.57% in MAE and 14.79% in MSE compared to top-performing models. Furthermore, AIGer also optimized the average training time, making it more practical for real-world applications.
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In essence, AIGer represents a significant step forward in modeling and representing And-Inverter Graphs. Its innovative approach to node embedding and information propagation allows it to capture the intricate details of logic circuits more accurately and efficiently than previous methods. This advancement has broad implications for the field of Electronic Design Automation, paving the way for more efficient and powerful chip designs. You can learn more about this research in the paper available at arXiv:2508.11991.
