TLDR: FeNN-DMA is a new RISC-V-based System-on-Chip designed for accelerating Spiking Neural Networks (SNNs) on FPGAs. It offers a fully programmable architecture with custom instructions for complex neuron models, synaptic delays, and compressed connectivity. With a bespoke DMA controller and a Python-based programming framework, FeNN-DMA efficiently simulates large SNNs, achieving high accuracy on spatio-temporal tasks like Spiking Heidelberg Digits and Neuromorphic MNIST, while maintaining comparable resource usage and energy efficiency to fixed-function accelerators.
In the rapidly evolving landscape of artificial intelligence, Spiking Neural Networks (SNNs) are emerging as a promising alternative to traditional Artificial Neural Networks (ANNs). SNNs mimic the human brain’s energy-efficient operation by communicating through sparse, event-based “spikes” rather than continuous data exchange. This approach significantly reduces the energy cost associated with the intensive matrix multiplications at the heart of ANNs, making SNNs particularly well-suited for tasks like keyword spotting and video classification.
However, the unique computational nature of SNNs presents a challenge for standard hardware accelerators like GPUs and TPUs, which are optimized for the high arithmetic intensity of ANNs. SNNs are often “memory-bound,” meaning their performance is limited by how quickly data can be moved, rather than how quickly calculations can be performed. Field Programmable Gate Arrays (FPGAs) are better suited for such memory-intensive workloads, and researchers have been exploring their use for SNN acceleration since the early 2000s.
Introducing FeNN-DMA: A Flexible RISC-V Solution for SNNs
A new research paper introduces FeNN-DMA, a novel, fully-programmable System-on-Chip (SoC) designed specifically to accelerate SNN simulations on modern UltraScale+ FPGAs. Developed by Zainab Aizaz, James C. Knight, and Thomas Nowotny, FeNN-DMA aims to overcome the limitations of existing SNN accelerators, which are often fixed-function, support only simpler neuron models, or cannot scale to larger, more complex networks.
FeNN-DMA stands out due to its RISC-V-based architecture, an open-source instruction set that allows for custom extensions, making it ideal for specialized accelerators. The system integrates a RISC-V scalar processor with a tightly-coupled, bespoke vector processor. This combination allows for both complex control flow and highly parallel computations, crucial for efficient SNN simulation.
Key Innovations and Capabilities
The FeNN-DMA architecture brings several significant contributions:
- Fully Programmable Accelerator: Unlike many fixed-function accelerators, FeNN-DMA is fully programmable, supporting complex neuron models, synaptic delays, and compressed connectivity using a customized Single Instruction Multiple Data (SIMD) instruction set. Each FeNN-DMA core can simulate up to 16,000 neurons with 256 million synapses, enabling the deployment of much larger and more intricate SNN models.
- Efficient Data Management: A custom Direct Memory Access (DMA) controller is central to FeNN-DMA’s efficiency. This controller efficiently streams synaptic weights from external DDR4 memory into on-chip Ultra RAM (URAM) and copies simulation outputs back. This “hides” the latency of external memory access, ensuring high throughput.
- User-Friendly Programming: To make SNN development accessible, the researchers developed a Python-based programming framework called PyFeNN. This framework allows users to define neuron models using a C-like language and SNNs using a PyTorch-like syntax, simplifying the process of creating and running SNN simulations on FeNN-DMA.
- Optimized Memory Usage: The design leverages the high-capacity Ultra RAM (URAM) blocks available on UltraScale+ FPGAs for large vector memories, while smaller Block RAMs (BRAMs) are used for lane-local memories, optimized for the specific access patterns of SNNs, especially with compressed weights and delays.
Performance and Real-World Impact
Deployed on the Kria KV260 FPGA, FeNN-DMA demonstrates impressive performance. A single-core design operates at 175 MHz, achieving state-of-the-art classification accuracy on challenging spatio-temporal datasets like Spiking Heidelberg Digits (SHD) and Neuromorphic MNIST (N-MNIST). For instance, on the SHD dataset, FeNN-DMA achieved an accuracy of 90.32%, a significant improvement over other FPGA-based accelerators. It also showed high accuracy on N-MNIST with extremely sparse and recurrently connected models, outperforming denser models on other systems.
The system’s ability to handle recurrent connectivity and synaptic delays—features common in advanced SNNs—is a key differentiator. These capabilities are crucial for tasks that require processing information over time, such as keyword spotting. While dedicated ASIC systems like Intel’s Loihi 2 might offer lower latency, FeNN-DMA provides a flexible, programmable, and energy-efficient solution on FPGAs with comparable resource usage to fixed-function systems, but with far greater capacity and model complexity support.
Also Read:
- New SNN Processor Boosts Edge AI with Synaptic Delay Emulation
- Neuromorphic AI Adapts in Real-Time on Intel Loihi 2
Looking Ahead
The researchers are already planning future enhancements, including connecting multiple FeNN-DMA cores to simulate even larger models and integrating the system with an event-based camera to create a complete spiking vision system. They also aim to explore training SNNs on FeNN-DMA using gradient-based methods like Eventprop, further expanding its utility beyond inference.
FeNN-DMA represents a significant step forward in making SNNs more practical and accessible for real-world applications, offering a powerful and flexible platform for neuromorphic computing research and development.
