TLDR: Researchers have developed a high-throughput Spiking Neural Network (SNN) processor that efficiently emulates synaptic delays for edge applications. The processor uses a multicore pipelined architecture and a spiking ring buffer to convert delayed computations into non-delayed equivalents. Prototyped on a PYNQ Z2 FPGA, it achieves 93.4% accuracy on the SHD benchmark with 104 samples/sec throughput and 282 mW power consumption, offering a cost-effective solution for complex temporal tasks in edge devices.
Researchers have developed a new Spiking Neural Network (SNN) processor designed to efficiently handle synaptic delays, a crucial element for advanced neural network dynamics, especially in edge computing applications. This innovation addresses a significant challenge in neuromorphic hardware: integrating complex temporal information processing without incurring high costs or resource overhead.
Synaptic delays are vital for how SNNs process information over time, mimicking the way biological brains integrate and process spatiotemporal data. While essential for achieving brain-like intelligence and biological accuracy, implementing these delays has traditionally been complex and resource-intensive, often leading to their omission in low-cost edge devices.
The new processor, detailed in the paper A High-Throughput Spiking Neural Network Processor Enabling Synaptic Delay Emulation, introduces a high-throughput architecture specifically designed to emulate these synaptic delays. It features a multicore pipelined architecture with parallel compute engines, enabling real-time processing of the computational demands associated with these delays.
At its core, the processor utilizes a modified Leaky Integrate-and-Fire (LIF) model, converting traditional delayed computations into non-delayed equivalents. This is achieved through a clever use of a spiking ring buffer, which effectively manages the timing of presynaptic spikes and their associated delays without requiring complex, resource-heavy delay lines.
The hardware architecture is composed of a configuration unit, external data interfaces, and four identical spiking computation cores. Each core includes a local controller, a memory pool, parallel Spiking Computation Engines (SCE), and a Spiking Direct Memory Access (SDMA) engine. The memory pool is critical, housing a Spiking Ring Buffer (SRB) for delay simulation, a Weight Memory (WTM) for synaptic parameters, and a Membrane Potential Memory (MPM). This design allows for efficient storage and retrieval of weights, membrane potentials, and historical spike data necessary for delay emulation.
The processor was prototyped as a System-on-Chip (SoC) on a PYNQ Z2 FPGA platform. Its performance was rigorously evaluated using the Spiking Heidelberg Digits (SHD) benchmark, a standard for keyword spotting tasks. The results were impressive: the processor achieved an accuracy of 93.4% in deployment. Furthermore, it demonstrated an average throughput of 104 samples per second at an operating frequency of 125 MHz, all while consuming a modest 282 mW of power. This performance significantly surpasses many existing neuromorphic architectures in terms of throughput and latency, making it a cost-effective solution for edge devices.
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This work represents a significant step forward in making biologically plausible SNNs with synaptic delay capabilities practical for real-world edge applications, such as always-on keyword spotting. By providing an efficient and flexible way to handle complex temporal tasks, this processor paves the way for more sophisticated and intelligent edge devices.
