TLDR: Flora is a three-stage rectilinear floorplanner that optimizes chip layout by considering both inter-module feedthrough and in-module component placement. It uses coarse-grained optimization for initial placement, fine-grained optimization for zero-whitespace and feedthrough reduction, and cross-stage optimization for efficient component placement within modules. Experimental results show Flora significantly reduces wire length and feedthrough while improving component placement density compared to existing methods.
In the intricate world of chip design, a crucial initial step known as floorplanning determines the layout of various components, or ‘modules,’ on a chip. This foundational stage significantly influences a chip’s Power, Performance, and Area (PPA) metrics. However, traditional floorplanning methods often fall short by focusing solely on the initial placement, neglecting subsequent stages like detailed component placement within modules and the routing of connections between them. This oversight can lead to inefficiencies, such as components not fitting properly or signals having to take circuitous paths, known as ‘feedthroughs,’ which can degrade performance.
Addressing these challenges, researchers Zhexuan Xu, Jie Wang, Siyuan Xu, Zijie Geng, Mingxuan Yuan, and Feng Wu have introduced a novel approach called Flora. Flora is a three-stage rectilinear floorplanner designed to be aware of both feedthrough and in-module component placement, aiming to optimize the entire physical design process from the outset. You can find the full research paper here: One Step Beyond: Feedthrough & Placement-Aware Rectilinear Floorplanner.
Flora’s Three-Stage Approach
Flora’s innovative design unfolds in three distinct stages, each contributing to a more optimized and integrated chip layout:
Stage 1: Coarse-grained Optimization
The first stage of Flora focuses on a broad, initial optimization. It uses techniques called ‘wiremask’ and ‘position mask’ to efficiently arrange modules, aiming to reduce the overall wire length (HPWL) and minimize feedthroughs. This stage ensures that modules are placed legally without overlapping, setting a solid foundation for subsequent refinements.
Stage 2: Fine-grained Optimization
Building on the coarse layout, the second stage refines the module shapes and allocates any remaining empty space, known as ‘whitespace.’ This stage is crucial for achieving a ‘zero-whitespace’ layout, meaning the chip canvas is fully utilized. By carefully resizing modules and converting them into more flexible ‘rectilinear’ shapes, Flora further reduces feedthroughs and creates better spaces for internal component placement. This process ensures that connections between modules are as direct as possible, improving efficiency.
Stage 3: Cross-stage Optimization
The final stage is where Flora truly shines by integrating component placement. It employs a fast tree search-based method to strategically place individual components, including large ‘macros’ and smaller ‘standard cells,’ within each module. After placing these components, Flora dynamically adjusts the module boundaries to accommodate them optimally. This cross-stage optimization ensures that the floorplan is not just a theoretical layout but one that genuinely supports the actual placement of all internal chip elements, leading to a higher ‘placement density’ (PD).
Also Read:
- Unsupervised AI Predicts Chip Design Flaws with High Accuracy and Speed
- VerilogDB: A New Standard for Training AI in Hardware Design
Impact and Results
Experimental results demonstrate Flora’s significant advantages over existing state-of-the-art floorplanning methods. Flora achieved an average reduction of 6% in Half-Perimeter Wire Length (HPWL), 5.16% in feedthrough pins (FTpin), and a remarkable 29.15% in feedthrough modules (FTmod). Furthermore, it showed a 14% improvement in component placement performance and consistently delivered layouts with zero whitespace, maximizing chip utilization.
While Flora’s comprehensive approach does result in a longer runtime compared to some traditional methods, this is a trade-off for its ability to integrate detailed placement and routing considerations into the early floorplanning stage. This holistic optimization ensures a more practical and efficient final chip design, laying a robust groundwork for future advancements in multi-stage chip design optimization.
