TLDR: VeriMaAS is a multi-agent AI framework that automates Register-Transfer Level (RTL) code generation for hardware design. It integrates formal verification feedback from Electronic Design Automation (EDA) tools directly into its workflow, allowing it to dynamically refine its code generation strategy. This approach improves synthesis performance by 5-7% and drastically reduces the need for extensive training data, making hardware design more efficient and less costly.
In the complex world of computer systems design, creating hardware designs, particularly at the Register-Transfer Level (RTL), is a specialized and challenging task. Traditional AI approaches often struggle here due to the scarcity of specific hardware description language (HDL) resources and the proprietary nature of Electronic Design Automation (EDA) tools. This often leads to expensive fine-tuning of AI models and complex manual orchestration of AI agents.
A new research paper introduces VeriMaAS, a groundbreaking multi-agent framework designed to automate the generation of RTL code. This innovative system aims to overcome the limitations of existing methods by integrating formal verification feedback directly into the AI workflow generation process. This unique approach significantly reduces the need for extensive training data and costly updates.
The core idea behind VeriMaAS is to dynamically guide AI agents using real-time design logs and error messages from RTL/EDA synthesis tools. Imagine an AI system that not only generates code but also understands if that code works correctly, based on feedback from the very tools engineers use to verify hardware. This feedback loop allows VeriMaAS to refine its reasoning strategy and improve the quality of the generated hardware designs.
How VeriMaAS Works
VeriMaAS operates by adaptively sampling a set of “reasoning operators” based on the design task and its difficulty. These operators are essentially different strategies an AI agent can use to generate code, such as Chain-of-Thought or Self-Refine. The system then takes the candidate designs and runs them through a synthesis and verification pipeline using tools like Yosys and OpenSTA. The resulting log and error messages are then fed back to a central “controller” module. This controller uses this feedback to decide whether to continue refining the design with more complex operators or to return the best current solution.
A key advantage of this method is its ability to learn from failures. If initial code attempts fail verification checks, VeriMaAS understands that the task requires more sophisticated reasoning and automatically escalates to more advanced operators. This adaptive process ensures that the system efficiently tackles tasks of varying complexity.
Impressive Results and Benefits
The researchers evaluated VeriMaAS on two state-of-the-art benchmarks, VerilogEval and VeriThoughts. The results are compelling: VeriMaAS improved synthesis performance by 5-7% for pass@k metrics compared to existing fine-tuned baselines. This means it generates correct and functional RTL code more effectively. Crucially, it achieves these gains with only a few hundred “training” examples for its controller, representing an order-of-magnitude reduction in supervision cost compared to traditional fine-tuning methods that require tens of thousands of samples.
Furthermore, VeriMaAS demonstrates flexibility beyond just accuracy. It can be re-optimized for different goals, such as Power, Performance, and Area (PPA) optimization. By adjusting its cost function to prioritize factors like area reduction, the framework can achieve significant reductions in area and runtime, showcasing its adaptability for various design objectives.
VeriMaAS also consistently improves performance across both benchmarks on top of various base Large Language Models (LLMs), including GPT-4o-mini, o4-mini, and Qwen models. This indicates that the multi-agent orchestration adds significant value, even when starting with high-performing base models.
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Looking Ahead
VeriMaAS represents a significant step towards more autonomous and efficient hardware design. By integrating formal verification feedback directly into AI workflows, it addresses critical challenges in RTL code generation, offering improved performance and reduced development costs. The researchers plan to further enhance the controller formulation and expand its integration with commercial EDA tools and PDKs for comprehensive synthesis and PPA optimization. You can learn more about this innovative framework by reading the full research paper available here.
