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HomeResearch & DevelopmentUnified Design for High-Performance Compute-In-Memory AI

Unified Design for High-Performance Compute-In-Memory AI

TLDR: CIMNAS is a novel framework that jointly optimizes neural network software, data quantization, and hardware parameters (device, circuit, architecture levels) for Compute-In-Memory (CIM) AI accelerators. By exploring a massive design space, CIMNAS achieves significant improvements in energy-delay-area product (EDAP) and efficiency for both RRAM-based MobileNet and SRAM-based ResNet50 architectures, all while maintaining high accuracy. This holistic approach overcomes the limitations of sequential optimization, leading to more efficient and high-performing AI hardware designs.

The rapid expansion of Artificial Intelligence (AI) applications and the increasing complexity of AI models are driving a significant demand for more energy-efficient hardware solutions. Traditional computing architectures often struggle to keep up with these demands, leading to the emergence of Compute-In-Memory (CIM) neural network accelerators as a promising alternative for energy-efficient AI processing.

However, maximizing the efficiency and performance of these CIM-based accelerators is a complex challenge. It requires simultaneously optimizing both the software (neural network model) and hardware design parameters. Manually tuning these parameters is practically impossible due to their sheer number and intricate interdependencies. This is where hardware-aware neural architecture search (HW-NAS) techniques come into play, offering an automated approach to design and optimize CIM-based AI systems.

Introducing CIMNAS: A Holistic Optimization Framework

A new framework called CIMNAS (Compute-In-Memory-Aware Neural Architecture Search) has been introduced to address this challenge. CIMNAS is unique because it performs a joint optimization across three critical areas: the neural network model, quantization policies, and a wide range of hardware parameters. This includes optimizations at the device, circuit, and architecture levels, ensuring a comprehensive approach to design.

The framework explores an incredibly vast design space, encompassing approximately 9.9 × 10^85 potential parameter combinations. To put that into perspective, it’s a number with 85 zeros! This extensive search space allows CIMNAS to find highly optimized solutions that traditional methods might miss.

Impressive Performance Gains

Experiments with CIMNAS, using the MobileNet model as a starting point and an RRAM-based CIM architecture, have shown remarkable results when evaluated on the ImageNet dataset. The framework achieved a significant reduction in the energy-delay-area product (EDAP) – a key metric for hardware efficiency – ranging from 90.1 to 104.5 times. It also improved energy efficiency (TOPS/W) by 4.68 to 4.82 times and area efficiency (TOPS/mm²) by 11.3 to 12.78 times. Crucially, these improvements were achieved while maintaining a high accuracy of 73.81%.

The adaptability of CIMNAS was further demonstrated by applying it to an SRAM-based ResNet50 architecture. In this scenario, it achieved an even more impressive reduction in EDAP, up to 819.5 times. Unlike many other state-of-the-art methods, CIMNAS focuses on EDAP optimization without sacrificing accuracy, generating diverse software-hardware parameter combinations for high-performance CIM-based neural network designs.

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Why Joint Optimization Matters

The core idea behind CIMNAS is that optimizing software and hardware independently or sequentially often leads to suboptimal results. Decisions made in one domain can significantly impact the efficiency of others. By integrating all these dimensions into a single, joint search process, CIMNAS avoids getting stuck in local minima and finds truly optimal configurations that balance accuracy with hardware efficiency.

The framework uses an evolutionary algorithm for its search, which is well-suited for large and complex design spaces. It also employs an accuracy predictor to quickly estimate performance, making the exploration of such a vast space practical. The hardware metrics are evaluated using a flexible simulator called CiMLoop, which provides fast and accurate estimations.

CIMNAS represents a significant step forward in automating the design of energy-efficient AI systems. Its ability to adapt to different neural network models, hardware configurations, and technology nodes makes it a robust and general-purpose framework for future AI hardware development. The source code for CIMNAS is openly available for further research and development. You can find more details in the full research paper: CIMNAS: A Joint Framework for Compute-In-Memory-Aware Neural Architecture Search.

Meera Iyer
Meera Iyerhttps://blogs.edgentiq.com
Meera Iyer is an AI news editor who blends journalistic rigor with storytelling elegance. Formerly a content strategist in a leading tech firm, Meera now tracks the pulse of India's Generative AI scene, from policy updates to academic breakthroughs. She's particularly focused on bringing nuanced, balanced perspectives to the fast-evolving world of AI-powered tools and media. You can reach her out at: [email protected]

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