TLDR: This research paper details a case study on applying the SpecC methodology for hardware/software co-design of a PCM-to-PWM converter, a key component in Class-D audio amplifiers. By systematically exploring hardware and software partitions, the study demonstrates how system-level co-design can achieve real-time performance while significantly reducing implementation costs compared to an all-hardware solution, offering early architectural insights and faster validation.
In the rapidly evolving world of semiconductor design, creating complex systems that are both cost-effective and high-performing is a significant challenge. Traditional design methods often struggle to keep pace with the increasing integration density and functional complexity of modern devices. This is where system-level design methodologies, particularly hardware/software co-design, offer a powerful solution. A recent research paper by Daniel G. P. Petrini Braz and Izaias da Silva Junior explores this approach through a case study of a PCM-to-PWM converter, a crucial component in Class-D audio amplifiers.
Understanding Hardware/Software Co-design
Hardware/software co-design is a methodology that involves the concurrent design of hardware and software components of a system. The goal is to optimize objectives like cost, performance, and time-to-market by carefully partitioning functionalities between hardware and software. This process typically involves several phases: specification, modeling, representation, estimation, partitioning, co-synthesis, co-simulation, and co-verification. This particular study focuses heavily on the estimation and partitioning phases, which are critical for making early architectural decisions.
The paper highlights that partitioning can be software-oriented (starting with a full software solution and moving parts to hardware) or hardware-oriented (starting with a full hardware solution and moving parts to software). The key is to divide the system into functional blocks and then map these blocks to either hardware (like an FPGA or ASIC) or software (running on a processor like a DSP or microcontroller), guided by an objective function that balances design goals.
The SpecC Methodology
At the heart of this research is the SpecC methodology, a robust framework designed to support high-level abstraction in system design. SpecC aims to refine an abstract design specification into an implementation model that runs on a target architecture. It employs four distinct models: a specification model, an architecture model, a communication model, and an implementation model. These models are progressively refined through transformations like architecture exploration, communication synthesis, and backend processes (hardware/interface synthesis and software compiling).
- Specification Model: This is a functional description of the system, translated into the SpecC language. It’s purely functional, without timing considerations, and helps in identifying potential parallelism.
- Architecture Model: Derived from architecture exploration, this model evaluates design alternatives and produces a hardware/software partition based on computational cost estimates and component characteristics.
- Communication Model: This stage adds system buses and maps abstract communication between components, leading to a more timing-accurate model.
- Implementation Model: The lowest level of abstraction, where hardware behaviors are translated to Hardware Description Languages (HDL) like VHDL, and software behaviors are converted to standard C++ for compilation to the target processor.
The SpecC language itself is an extension of C, incorporating features necessary for embedded systems design, such as concurrency modeling, hierarchy, communication, synchronization, and timing. The System-on-Chip Environment (SCE) provides tools for modeling, synthesis, and validation within this methodology.
Case Study: The PCM/PWM Converter
To demonstrate the benefits of this system-level approach, the researchers applied the SpecC methodology to an audio PCM-to-PWM converter, a core component of Class-D audio amplifiers. Class-D amplifiers are known for their high efficiency (around 90%) compared to traditional Class A or AB amplifiers, which dissipate significant power. The converter’s role is to transform a Pulse Code Modulation (PCM) signal into a Pulse Width Modulation (PWM) signal, a process that requires sophisticated signal processing to reduce the operational frequency to a feasible level for consumer electronics.
The conversion algorithm involves four sequential stages: up-sampling, linearization, noise shaping, and waveform generation. The original implementation of this converter in Verilog HDL on an FPGA met timing requirements but incurred high costs due to the large number of programmable logic elements needed.
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Results and Benefits of Co-design
The study began by converting the existing C program of the converter into a SpecC program, progressively refining it into a program finite-state machine structure compatible with SCE’s automatic tools. A crucial phase was architecture exploration, where the computational cost of the system was estimated across different processing elements (DSP, Microprocessor, Microcontroller, and dedicated Hardware/FPGA).
The analysis revealed that only a high-end microprocessor (Pentium) or a full hardware implementation could meet the real-time performance requirement (4.3 seconds playback duration for the audio file). However, the Pentium option was deemed too expensive and deviated from the co-design premise. The full hardware solution, while performant, was also costly. This led to exploring hybrid hardware/software partitions.
By analyzing different mappings of the converter’s behaviors (S0, S1, S2, S3, LINE, MOLD) to either DSP (software) or FPGA (hardware), the researchers identified an optimal solution. Mapping the “MOLD” (noise shaping) behavior to hardware, while keeping others in software on a DSP, satisfied the timing constraints and significantly reduced the overall cost compared to an all-hardware implementation. This co-design approach resulted in a total cost of $10.60, compared to $35.00 for a 100% hardware solution and $9.00 for a 100% software solution on a DSP (which failed to meet timing).
The SpecC/SCE methodology offered several advantages: informed architectural decisions through estimates, automatic refinement steps, fast system-level simulation for early validation, and feasible manual exploration due to a manageable number of system behaviors. While the specific version of the tool had limitations (e.g., no automatic partitioning algorithms, limited exploration metrics), the overall approach proved highly effective.
Comparing this co-design flow to a traditional Register-Transfer Level (RTL) design flow, the co-design approach demonstrated lower implementation cost, significantly faster simulation times at the system level, and reduced refinement effort. It also highlighted the potential for substantial code reduction (800 lines of SpecC/C vs. ~10,000 lines of Verilog for the original RTL design). Although a final implementation was not produced in this study, the findings strongly suggest that system-level co-design, especially with methodologies like SpecC, is highly recommended for increasingly complex systems, offering actionable estimates and accelerating development cycles. You can read the full paper here.
