TLDR: MAHL is a novel framework that uses a multi-agent Large Language Model (LLM) system to automate and optimize the hierarchical design of chiplets for AI workloads. It addresses common LLM limitations like flattened designs, high validation costs, and imprecise parameter optimization through six collaborative agents. The framework significantly improves design generation accuracy and achieves competitive Power, Performance, and Area (PPA) results compared to conventional LLMs and expert-based methods.
As artificial intelligence workloads continue to grow in size and complexity, the challenge of designing efficient computing hardware becomes increasingly significant. Traditional chip design methods struggle with the high dimensionality of modern AI algorithms, encompassing various computing cores, array sizes, and memory hierarchies. While machine learning has already begun to assist in agile chip design, the recent advancements in Large Language Models (LLMs) offer a promising avenue for further innovation, particularly in the realm of 2.5D integration – an advanced packaging technique that helps reduce area overhead and development costs for integrated circuits.
However, relying solely on LLMs for chiplet design presents several hurdles. These include the tendency of LLMs to generate ‘flattened’ designs (where all code is in one block, lacking modularity), high validation costs due to inaccurate code, and difficulties in precisely optimizing design parameters. To tackle these challenges, researchers from the University of Minnesota – Twin Cities have introduced MAHL: Multi-Agent LLM-Guided Hierarchical Chiplet Design with Adaptive Debugging. This innovative framework aims to streamline the chiplet design process by leveraging a collaborative multi-agent system.
Introducing MAHL: A Collaborative AI Approach to Chiplet Design
MAHL is a hierarchical LLM-based framework designed to generate chiplet designs efficiently, with a focus on optimizing Power, Performance, and Area (PPA). It achieves this through the coordinated efforts of six specialized agents, each handling a critical aspect of the design workflow:
- AI-Hardware Hierarchical Parser: This agent takes a user’s natural language input describing an AI algorithm and breaks it down into computational and interconnection modules. It then maps these to appropriate hardware modules, using LLMs and a library of existing components. If a component isn’t found, it can interact with a human to get the necessary specifications.
- Hierarchical Module Description Generator: For mapped hardware modules, this agent retrieves hierarchical descriptions from a library. For new or unmapped modules, a duo-agent system (a generator LLM and an evaluator LLM) creates and refines structured descriptions, ensuring they meet format and completeness requirements.
- Retrieval-Augmented Code Generator: This agent takes the hierarchical module descriptions and generates Hardware Description Language (HDL) code. It prioritizes code reuse by dynamically querying a Code Library for high-quality, pre-verified code snippets, only generating new code when necessary.
- Diverseflow Validator: A crucial component for debugging, this agent integrates simulation and synthesis tools with a multi-round debugging strategy. It generates testbenches using LLMs and retrieves existing ones. To prevent getting stuck on a single error, it injects controlled ‘noise’ into prompts, encouraging diverse debugging attempts. A ‘Thinker’ LLM diagnoses issues, and a ‘Coder’ LLM applies fixes.
- Multi-Granularity Design Space Explorer: Chiplet design involves a vast number of possible configurations. This agent combines the strengths of LLMs for coarse-grained exploration of the design space with analytical techniques for fine-grained refinement. It identifies optimal hardware parameters by analyzing PPA metrics and provides feedback for further optimization.
- Configurator: For the final physical layout, this LLM-based agent automatically generates and revises configuration files for tools like OpenROAD, tuning parameters such as wire length, spacing, and chip size to ensure a successful layout.
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Performance and Impact
Experiments demonstrate that MAHL significantly improves the accuracy of generating both simple RTL (Register-Transfer Level) designs and complex real-world chiplet designs. For simple RTL designs, the framework improves the average Pass@1 success rate by 44.67% compared to conventional methods. For real-world chiplet designs, evaluated by Pass@5, MAHL achieves a remarkable increase from 0 to 0.72 when compared to conventional LLMs under the best-case scenario. This means MAHL is far more successful at producing functional and correct designs.
Furthermore, when compared to state-of-the-art expert-based frameworks like CLARIE, MAHL achieves comparable or even superior PPA results for specific optimization objectives. For instance, MAHL-generated designs showed an average latency reduction of 16.08% in high-performance mode and an impressive 83.96% area reduction in compact-area mode compared to human-designed chiplets. While LLM-based generation tends to excel at primary design objectives, the research notes that there’s still room for improvement in achieving a comprehensive trade-off across all hardware design factors, such as power density.
The MAHL framework represents a significant step forward in automating chiplet design for AI applications. By decomposing complex tasks into manageable submodules and leveraging the power of multi-agent LLMs, it addresses key limitations of direct LLM application, paving the way for more efficient and optimized hardware development. You can find more details about this research in the paper available at arXiv.org.
