TLDR: Faver is a new middleware that significantly improves the accuracy of LLM-generated hardware description language (RTL) code for chip design. It bridges the gap between high-level software verification and complex hardware timing by using a function-abstracted, verifiable framework. This allows LLMs to write high-level Python/C verification code that co-simulates with RTL, leading to up to a 14% increase in generation correctness.
The paper introduces Faver, a new approach to improve the accuracy of generating Register Transfer Level (RTL) code using Large Language Models (LLMs). RTL design is a crucial but labor-intensive step in creating integrated circuit (IC) chips. While LLMs show promise in automating this process, they often struggle with accuracy due to the significant difference between high-level specifications and the detailed, time-sensitive nature of RTL code, as well as a lack of extensive training data.
Faver addresses these challenges by integrating a “design with verification” methodology, which mirrors how human engineers work. This approach involves verifying the design as it’s being created to catch errors early. Traditional methods for LLM-based verification, such as having the LLM act as a judge or generate RTL testbenches, have not been very effective. Generating RTL testbenches can be as complex as writing the RTL design itself, and testbench data is even scarcer.
A more natural idea is to use high-level languages like Python or C for verification, as LLMs are generally better at handling these languages. However, simply asking an LLM to write Python code for RTL verification also leads to issues. The core problem lies in the different ways hardware and software handle functionality, particularly concerning time-dependent variables like clocks, registers, and reset signals, which are inherent to hardware but absent in standard Python/C. Designing effective test stimuli that account for both high-level temporal semantics and bit-level precision is also a significant hurdle.
Faver overcomes these difficulties by acting as a “function abstracted verifiable middleware.” It allows LLMs to focus on writing high-level, functional verification code by encapsulating the complexities of hardware-software differences within a function-class package. This package maps hardware concepts like registers to global variables and treats clock inputs as “events” (a “call step” action), making it easier for LLMs to generate Python code that can co-simulate with Verilog.
How Faver Works
The Faver framework operates in four key steps:
1. The LLM generates the initial RTL code from a specification.
2. The LLM then creates a higher-level verification specification from the design specification. This involves preserving input/output ports, abstracting the core functionality, and analyzing boundary conditions (like bitwidth constraints).
3. Using this verification specification, the LLM generates a functional reference model and test stimuli. Faver provides a class template that helps the LLM structure this Python code, including init, reset, and step functions to manage state and sequential inputs. Test stimuli generation combines LLM-driven high-level planning with rule-based refinement for low-level data stream accuracy, ensuring proper resets and boundary checks.
4. A Python-Verilog co-simulation is performed. If mismatches occur, a detailed report is generated and fed back to the LLM for iterative refinement, with a set iteration threshold to prevent infinite loops.
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Experimental Results
Experiments conducted with various LLMs, including DeepSeek-R1-0528, Kimi K2, and Qwen2.5-7B-SFT, on benchmarks like RTLLM and Verilog-Eval, showed significant improvements. Faver boosted the model’s RTL generation accuracy by up to 14%. For instance, DeepSeek-R1-0528’s sys sel pass@1 on the RTLLM dataset improved from 74% to 83%. The research highlights that direct Python-based verification without Faver’s middleware often yields inconsistent or limited gains, underscoring the value of Faver’s functional abstraction.
An ablation study further confirmed the importance of both Faver’s reference model generation and hierarchical test stimuli components, showing that each contributes notably to the overall accuracy gains. The analysis also demonstrated that Faver’s accurate verification feedback leads to a steady improvement in code correctness over iterations, unlike the more random fluctuations seen without it.
This innovative middleware offers a promising path to liberate the least automated stage in chip design, making LLM-based RTL generation more reliable and efficient. You can read the full research paper here: Faver: Boosting LLM-based RTL Generation with Function Abstracted Verifiable Middleware.
