TLDR: A new reinforcement learning and relational graph convolutional neural network approach significantly improves analog integrated circuit floorplanning by making it routing-aware. This method incorporates higher grid resolution, precise pin information, and dynamic routing resource estimation, leading to a 13.8% reduction in dead space, 40.6% reduction in wirelength, and a 73.4% increase in routing success compared to previous learning-based techniques.
Designing analog integrated circuits (ICs) is a highly specialized and challenging task. Unlike their digital counterparts, analog ICs have strict requirements due to noise, parasitics, and specific topological needs. A major hurdle in automating this process is the close relationship between floorplanning (placing components) and routing (connecting them). A compact floorplan might seem ideal, but if it’s impossible to route, it’s useless.
Researchers Davide Basso, Luca Bortolussi, Mirjana Videnovic-Misic, and Husni Habal have introduced a novel solution to this problem. Their work, detailed in their paper Advancing Routing-Awareness in Analog ICs Floorplanning, presents an automatic floorplanning engine that uses reinforcement learning (RL) combined with relational graph convolutional neural networks (R-GCNs). This engine is specifically designed to generate floorplans that are inherently easier to route.
Key Innovations for Smarter Floorplanning
The new approach incorporates several significant enhancements to achieve its routing-aware capabilities:
- Higher Resolution Grid: The floorplanning grid resolution has been dramatically increased from 32×32 to 256×256. This allows for much more precise placement of analog devices, accommodating finer granularity in the layout space.
- Detailed Pin Information: The system integrates precise pin data into both the graph representation and the RL agent. This helps the agent better understand the layout problem, leading to more accurate estimations of wirelength.
- Dynamic Routing Resource Estimation: A dynamic mechanism estimates and reserves routing space around each block. This padding is based on the number and direction of pins, as well as routing grid constraints, ensuring enough room for connections and reducing congestion.
- Routing-Driven Reward Scheme: The RL agent’s reward system has been revised to actively prioritize the generation of routing-friendly floorplans. It focuses on optimizing wirelength without sacrificing area efficiency.
- Custom A* Routing Engine: To validate the floorplans, a custom A*-based rip-up and reroute routing engine was developed. This prototype assesses the routability of the proposed floorplans and ensures compliance with design rules.
Impressive Performance Gains
When tested in a simulated environment, the proposed routing-aware floorplanning engine demonstrated substantial improvements compared to previous learning-based state-of-the-art techniques. It achieved a 13.8% reduction in dead space, a 40.6% reduction in wirelength, and a remarkable 73.4% increase in routing success. For complex circuits like a 24-block delay line, where previous methods failed to produce a fully working routing solution, the new system achieved successful routing in 76% of cases in an average of 48.7 seconds.
The training of the RL agent utilized a hybrid curriculum learning approach, starting with simpler circuits and progressively sampling more complex ones. The dataset included 10 circuits based on the Infineon 130nm Commercial Technology node, encompassing a variety of designs such as operational transconductance amplifiers (OTAs), biasing circuits, and clock resynchronization circuits.
Also Read:
- Enhancing AI Model Alignment by Resolving Feedback Inconsistencies
- Enhancing LLM Multi-Agent Reasoning Through Strategic Self-Play
Looking Ahead
This research represents a significant step forward in automating analog IC layout design. By making floorplanning inherently routing-aware, the system addresses a critical concern among layout engineers and paves the way for more efficient and reliable analog chip development. Future work will focus on further enhancing the routing engine and integrating it into a feedback loop with the RL placement agent for continuous improvement.
