TLDR: Researchers have developed a new voltage-mode Winner-Take-All (WTA) circuit for neuromorphic systems, designed for high speed and low power consumption. Simulated in IBM 65 nm technology, the circuit processes 1000 inputs with 34.9 µW power dissipation and 10.4 ns latency. It features configurable k-winner and hysteresis properties, asynchronous operation, and implements a softmax function for efficiency. The circuit’s utility is demonstrated in spatial filtering and image classification, making it well-suited for energy-constrained neuromorphic chips.
Neuromorphic computing, a field focused on building computer systems inspired by the human brain, is making significant strides in enabling on-device learning with remarkable energy efficiency. A crucial component in these brain-inspired systems is the Winner-Take-All (WTA) circuit. This circuit is designed to identify and select the strongest input among many competing signals, effectively mimicking how neurons compete in biological neural networks.
Traditional methods for identifying a ‘winning’ signal can often become a bottleneck, slowing down learning and classification processes. This is where WTA circuits become indispensable, performing local competitions to select a single winning output node while suppressing all others. While many WTA circuits exist, they often face trade-offs between stability, precision, compactness, and energy efficiency. Analog WTA circuits, despite some stability challenges compared to their digital counterparts, generally offer more compact and energy-efficient designs, making them ideal for mobile and energy-constrained platforms.
Researchers have recently introduced a novel voltage-mode Winner-Take-All (WTA) circuit specifically designed for neuromorphic applications. This new circuit stands out due to its high operating speed and exceptionally low energy consumption. Unlike many existing circuits, its voltage-mode operation eliminates the need for additional conversion circuitry when integrated with other signal processing integrated circuits (ICs). Furthermore, storing information in voltage mode is more energy-efficient than current mode, which requires continuous current supply.
Key features of this proposed circuit include its asynchronous operation and parallel input processing, along with high drive strength achieved by buffering all outputs. It also offers configurable sensitivity, allowing for adjustments to signal variations and noise, and uniquely supports multiple winners, expanding its utility for various neural algorithms like pattern matching. A significant innovation is its implementation of a softmax function, which efficiently suppresses current in losing cells while maximizing it in winning ones, leading to very low power consumption even when scaled to hundreds of cells.
The circuit’s design is a variation of a known current conveyor circuit, modified to provide voltage-mode output. This is achieved by incorporating a current comparator that compares the mirrored current from each branch to a fixed reference, resulting in a voltage output that maintains a normalized exponential relationship with the input. This relationship is crucial for maximizing the difference between inputs, generously rewarding the highest value, and penalizing the lower ones, which contributes to its low power consumption.
Simulations of the proposed WTA circuit, conducted using IBM 65 nm technology, demonstrated impressive performance. It requires a minimum voltage difference of just 4 millivolts between two cells to cause a state flip. The response time was measured at 6.36 nanoseconds, notably independent of the number of cells, even when scaled up to 1000. This stability is attributed to the output buffering and the efficient current direction via the softmax operation. The circuit also incorporates a hysteresis mechanism, enhancing network stability and preventing premature winner selection, achieved through a local excitatory feedback.
The utility of this WTA circuit extends to various applications. It can effectively perform spatial filtering, such as removing image backgrounds and binarizing images by zeroing pixels below a certain threshold and setting others to maximum. This binarization is particularly useful for bio-inspired algorithms like Hierarchical Temporal Memory (HTM). Additionally, the circuit was successfully used to perform the softmax operation within a densely connected convolutional neural network for image classification, achieving 90% testing accuracy on the CIFAR-10 dataset. The circuit accurately identified winning classes from analog signals derived from the network’s output.
In terms of overall performance, the circuit dissipated only 34.9 microwatts of power while processing 1000 inputs, with a nominal latency of 10.4 nanoseconds. Even under worst-case conditions (including variations in fabrication process, voltage supply, and temperature), the power consumption averaged 40 microwatts, and latency averaged 11.19 nanoseconds. This performance highlights its suitability for scalable, high-speed, and low-power neuromorphic systems. For more technical details, you can refer to the full research paper here.
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In conclusion, this voltage-mode WTA circuit represents a significant advancement for neuromorphic chips, particularly those requiring efficient WTA functionality, such as spiking neural networks and hierarchical temporal memory. Its combination of high speed, low power consumption, scalability, and configurable features makes it a promising component for the next generation of brain-inspired computing hardware.
